Pipelined RISC-V CPU
2024The Workshop
A pipelined RISC-V CPU supporting 40+ instructions, with full hazard handling.
- Designed and implemented a pipelined RISC-V CPU supporting 40+ instructions.
- Comprehensive hazard detection and handling across the pipeline.
- Built and simulated in Verilog using Vivado.
- Verilog
- Vivado
- Computer Architecture